In FPGAs, it is useful to have static RAM in the logic blocks. Sometimes this RAM is used for general purposes and only needs to have a single port. In other instances, to give the designer greater flexibility to implement FIFOs, the SRAM needs to have dual port capability so that simultaneous read and write operations using two different ports can be accomplished. In other instances, a logic block has more memory cells than are needed, but the designer can use all the cells if the memory could be split into two separate RAM memories, each with its own I/O address and data inputs and data output, and each configured to be single port.
Thus a need has arisen for a SRAM architecture which can be switched between dual port and single port configurations, and which can be either a x1 configuration where all cells are unified in a single memory or a x2 configuration where the memory cells available are split into two separate RAMs, each single port and each with its own I/O.